Logic Synthesis for Finite State Machines Based on Linear Chains of States: Foundations, Recent Developments and Challenges By Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
English | PDF | 2018 | 228 Pages | ISBN : 3319598368 | 6.77 MB
This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit.