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Cadence Allegro and OrCAD 17.20 HF026 Update

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Cadence Allegro and OrCAD 17.20 HF026 Update

Cadence Allegro and OrCAD 17.20 HF026 Update | 1.6 Gb

Cadence Design Systems, Inc. has released an update (HF026) to OrCAD Capture, PSpice Designer and PCB Designer 17.2-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.

1765398 ADW DATAEXCHANGE Duplicate MPNs are created when updating MPN classification properties with data exchange
1780147 ADW DBEDITOR 'Associate Footprint from Tree' does not log the information
1790134 ALLEGRO_EDITOR DATABASE Correct spelling in Layer Function definition
1792345 ALLEGRO_EDITOR DATABASE Pastemask is added to bottom layer on backdrilled pins
1792930 ALLEGRO_EDITOR DATABASE Uprev required for all libraries and padstacks to use release 16.6 DRA in release 17.2-2016
1781203 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu
1797422 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu
1770694 ALLEGRO_EDITOR INTERFACES Incremental IDX does not place unplaced components
1776791 ALLEGRO_EDITOR INTERFACES STEP file not displayed in PCB Editor for mapping
1783515 ALLEGRO_EDITOR INTERFACES PCB Editor reading step model incorrectly
1781485 ALLEGRO_EDITOR MANUFACT Setting ipc2581attrpath results in error 'E- ipc2581attrpath: Variable not defined'
1772713 ALLEGRO_EDITOR MULTI_USER Allegro Symphony Server rejects group moves
1789853 ALLEGRO_EDITOR MULTI_USER Symphony Server rejects updates and hangs frequently
1725591 ALLEGRO_EDITOR OTHER File - Export PDF crashes on the design attached
1736324 ALLEGRO_EDITOR OTHER Export - PDF fails to export PDF
1794071 ALLEGRO_EDITOR PLACEMENT The placement of component is very slow and takes around 3 to 5 minutes per component.
1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape.
1760146 ALLEGRO_EDITOR SHAPE Void offset in Artwork but not in board for a particular instance only
1770372 ALLEGRO_EDITOR SHAPE Overlapping shapes merged in artwork shifts void causing a manufacturing short
1793419 ALLEGRO_EDITOR SHAPE Unexpected shape void in artwork in release 16.6
1796666 ALLEGRO_EDITOR SHAPE DRCs for out-of-date shape while placing single via
1786386 APD EXPORT_DATA Exported dra and pad files do not have right stackup
1765673 APD SHAPE Shape in Cu1 and Cu3 cannot void correctly
1782418 APD SHAPE Artwork is showing unnecessary horizontal lines
1778366 CONCEPT_HDL CHECKPLUS CheckPlus not printing logic design name
1723855 CONCEPT_HDL CORE Cannot use Rename Signal for unnamed wire segment if the wire has a branch to the same instance
1755174 CONCEPT_HDL CORE Unable to create XNETs on the read-only blocks
1765533 CONCEPT_HDL CORE Strokes are slow to respond in release 17.2-2016
1780253 CONCEPT_HDL CORE In Windows mode, with copy command still active and symbol on cursor, DE-HDL stops responding on pressing Delete key
1785069 CONCEPT_HDL CORE Warning box for SPCOCN-2251 needs to be resized and the text formatted correctly
1786030 CONCEPT_HDL CORE Packager fails in release 16.6 but runs successfully in release 17.2-2016
1788077 CONCEPT_HDL CORE Creating new window (new tab) in DE-HDL resets view of original window
1788591 CONCEPT_HDL CORE Wrong pin number displayed after running packager
1776774 CONCEPT_HDL CREFER CRefer crashes without error entry in log file
1328320 CONCEPT_HDL PDF Cannot select/search sig_name in published PDF
1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish
1758122 CONSTRAINT_MGR ANALYSIS Extracted topology for a differential pair is missing a pin-to-pin connection in the top file
1786161 CONSTRAINT_MGR CONCEPT_HDL Random crashes in release 17.2-2016 while working on the schematic editor along with Constraint Manager
1788877 CONSTRAINT_MGR DATABASE Constraint Manager API cmxlImportFile looks for sub-string during replace mode and not explicit names
1800263 CONSTRAINT_MGR OTHER DE-HDL and CM crash when deleting regions
1792000 CONSTRAINT_MGR UI_FORMS Data type of constraint not shown in GUI
1744828 FSP CAPTURE_SCHEM Button appears during 'Generate OrCAD Schematics'
1747568 ORBITIO OTHER Import of .oio file in SiP Layout takes a long time
1765229 PSPICE AA_FLOW Not able to run PSpice MC after setting Assign Tolerance
1770174 PSPICE MISC Issues with DMI Template Code Generator

About Allegro and OrCAD 17.2-2016. The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
- OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
- New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.
- New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
- OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors’ productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
- OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
- Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
- PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.

Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located here

About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.

Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20 HF026 Update
Supported Architectures: 64bit
Website Home Page : www.cadence.com
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above
Size: 1.6 Gb
Cadence Allegro and OrCAD 17.20.000-2016

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Cadence Allegro and OrCAD 17.20 HF026 Update